サトウ トモアキ
  佐藤 友暁   経済学部 経営情報学科   教授
■ 標題
  A Circuit Design for IEEE 802.11ac by ASIC-FPGA Co-Design
■ 概要
  High-speed wireless networks like IEEE 802.11ac are essential for smooth cooperation between mobile devices and cloud services. Security measures are also essential at the same time. However, packet processing with the throughput of IEEE 802.11ac has the problem that it cannot be executed on a mobile CPU. In addition, since the use of an application specific integrated circuit (ASIC) cannot add new circuits and change circuits, it cannot cope with a new attack required by an intrusion prevention system (IPS). In this paper, ASIC-FPGA co-design for IPS processing is proposed for solving these problems and used for developing a firewall unit which is needed for IPS processing. As a result, although it is possible to change circuits, it is clarified that the throughput necessary for IEEE 802.11ac is greatly exceeded.
   共著   Proc. of ISMAC 2017   電子情報通信学会   pp.89-92   2017/08