サトウ トモアキ
  佐藤 友暁   経済学部 経営情報学科   教授
■ 標題
  Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
■ 概要
  Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAs, wave-pipeline techniques can be introduced for further high-throughput processing. In order to further improve the performance of wave-pipelines on the FPGAs, fine-tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
   共著   Proc. of ISCIT 2018   IEEE   pp.204-207   2018/09