サトウ トモアキ
  佐藤 友暁   経済学部 経営情報学科   教授
■ 標題
  Throughput of a Firewall Unit on FPGAs developed by the RTL Design Methodology
■ 概要
  The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAs (field-programmable gate arrays) which are developed by the RTL (register-transfer level) design methodology. As an application of the FPGAs for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.
   共著   Proc. of iEECON 2017   pp.423-426   2017/03